It is well known in the art of computer architecture that instructions to be executed by a processor may be first fetched into an instruction decoder and then decoded. In particular, an instruction may specify, in an encoded form in one portion or field, of the instruction, an operation which is to be performed. Another portion of the instruction may specify the operands on which the operation is to be performed. The operation and the operands are determined by decoding the instruction in portions, before the operation is performed. For more background information, the reader is referred to Computer Architecture: A Quantitative Approach, by Patterson and Hennessy (Morgan Kaufman, 1990), Chapter 5.
In a processor decoder architecture of the type disclosed in co-pending and commonly assigned U.S. patent application Ser. No. 08/445,563, entitled "TAGGED PREFETCH AND INSTRUCTION DECODER FOR VARIABLE LENGTH INSTRUCTION SET AND METHOD OF OPERATION", filed on even date herewith, processor instructions to be decoded are first fetched (e.g., from the processor memory or from an instruction cache) and stored into a circular "line buffer". The address in the line buffer at which the first byte of a fetched instruction is stored is determined by the least significant bits of the address in the memory at which the instruction begins. Then, the bytes of the instruction are stored into the line buffer sequentially. When the last byte of the line buffer is reached, the next byte of the instruction "wraps around" to be stored into the first byte of the line buffer.
For example, as shown in FIG. 1, a line buffer 100 may have sixteen locations (i.e., locations with addresses 0h to Fh). An instruction of length Ah (i.e., bytes 0h through 9h), beginning at location FA38h in processor memory, would be stored into the line buffer at line buffer locations 8h, 9h, Ah, Bh, Ch, Dh, Eh, Fh, 0h, and 1h, as also shown in FIG. 1.
What is desired is a circuit which can be used to maintain a first pointer which always points to the beginning processor memory address of an instruction currently being decoded; and a second pointer which points to a location in a line buffer. The second pointer may be incremented as the instruction is "consumed" by the decoder, to point to the next instruction portion to be processed by the decoder. In any event, however, the second pointer should point to the beginning of an instruction in the line buffer when the decoder begins to process that instruction.